Arrays of fuse devices, and more particularly, arrays fabricated utilizing emitter coupled logic (ECL) technology are well known in the prior art. Such fuse arrays are suitable for forming programmable read only memories (PROMs) and programmable logic arrays (PLAs). Emitter coupled logic technology is particularly well suited for extremely fast devices since opposing transistors are forced to share a limited amount of current made available by a current source in such a manner that neither of the two transistors ever saturate.
One fuse element suitable for use in such devices is the so-called lateral fuse, such as the metal fuse depicted in FIG. 1 which may be formed of any suitable metal or interconnect material, typically titanium tungsten. When utilizing a lateral fuse device with ECL circuitry, the most appropriate fuse array configuration is the OR configuration, since the ECL input (which has limited current sink capability) will only sink transient (capacitive) current. Such an OR array is shown in the schematic diagram of FIG. 2. FIG. 2 shows a plurality of N columns 204-1 through 204-N each containing a current source 206-1 through 206-N tending to pull nodes 209-1 through 209-N low. Row line 201 serves to receive an input signal which is supplied to the base of transistors 202-1 through 202-N, having their collectors connected to VCC and their emitters connected through fuses 203-1 through 203-N to node 209-1 through 209-N. Fuses 203-1 through 203-N are capable of being individually programmed (i.e., altered from their initial state of being short circuits to a programmed state of being an open circuit) in a well known manner, for example by providing a high signal on row line 201 and providing a programming voltage in excess of VCC and typically 10 volts to the collectors of those of transistors 202-1 through 202-N associated with those of fuses 203-1 through 203-N which are desired to be programmed.
A single current source circuit containing transistor load device 207 and resistor 208 serves to supply current from a positive supply voltage VCC through diodes 205-1 to 205-N to nodes 209-1 through 209-N. Resistor 208 supplies current required by current sources 206-1 through 206-N when such current is not supplied by transistors 202-1 through 202-N. This occurs when row line 201 goes low, or a fuse 203-1 through 203-N associated with a particular current source 206-1 through 206-N is blown (open). Transistor 207 serves to limit the voltage across resistor 208 when more than one current source 206-1 through 206-N is drawing current from VCC at the same time.
One embodiment of a circuit suitable for providing appropriate driving signals to row line 201 is shown in the schematic diagram of FIG. 3. Row driver circuit 300 is an ECL circuit utilizing a first current source 310 to control pull up transistors 306 and 314 which serve to supply pull up current to ROW line 308 and ROW line 315, respectively. Circuit 300 includes a second current source 312 which serves to control pull down transistors 304 and 313 which serve to sink current from ROW line 308 and ROW line 305, respectively. An input signal defines whether it is desired to source current to row line 315 (i.e., apply a logical one signal to row line 315) or sink current from row line 315 (i.e., apply a logical zero signal to row line 315), and simultaneously apply the inverse binary signal to ROW line 308. Input lead 301 is connected to the base of transistor 302, having its collector connected to VCC. The emitter of transistor 302 is connected to pull down current source 303 and to the bases of transistors 304 and 305. In a similar manner, a bias voltage VBB having a value approximately between a logical zero and a logical one voltage level of the input signal applied to input lead 301, is applied to the base of transistor 316. The collector of transistor 316 is connected to VCC, and its emitter is connected to pull down current source 317 and to the bases of transistors 311 and 313. Thus, as is well known to those of ordinary skill in the art of ECL circuit design, when the input signal applied to input lead 301 is low (i.e, less than VBB) transistors 304 and 305 are turned off and transistors 311 and 313 are turned on. With transistors 304 and 305 turned off, current is supplied from VCC through resistor 307 to the base of transistor 306, turning on transistor 306 and applying current to ROW line 308, thus providing a logical one signal to ROW line 308. Similarly, with transistors 311 and 313 turned on, the voltage applied to the base of row line pull up transistor 314 is low, keeping row line pull up transistor 314 turned off. At the same time, transistor 313 is turned on, thus pulling row line 315 low, to a logical zero value.
Since ECL input buffer 300 includes active pull up transistors 306 and 314 having low output impedance, and pulls down by way of current source 312 having medium to high output impedance, circuit 300 is very effective in driving the high input impedance of row line 201 of the emitter follower array of FIG. 2. Since no DC current is sourced by row line 201 of FIG. 2, ECL buffer 300 of FIG. 3 need only sink capacitive current from row line 201. This is acceptable, since the medium to high input impedance of circuit 300 is capable of providing only small currents. Conversely, a small DC current is sunk by row line 201, in the amount of the sum of the current supplied current sources 206-1 through 206-N, divided by the current gain or beta of transistors Q202-1 through Q202-N, respectively. This small amount of DC current which is sunk by row line 201 is easily provided by the low output impedance of transistors 306 and 314 of the buffer of FIG. 3.
An alternative to the lateral fuse device of FIG. 1 is the so-called vertical fuse, as depicted in cross-sectional view in FIG. 4a. Vertical fuse 40 of FIG. 4a is well known in the prior art and includes buried collector 41, substrate 42, base region 43, and emitter 44. Base region 43 is doped to an opposite conductivity type as buried collector 41, substrate 42, and emitter 44, thereby forming a vertical bipolar transistor. When used as a fuse device, emitter 44 and buried collector 41 serve as the two leads of the fuse device and, in its unprogrammed state, remains an open circuit. However, fuse device 40 is capable of being programmed, for example by the application of a sufficient amount of programming current applied at a sufficiently high voltage to cause breakdown of the PN junction formed between emitter 44 and base 43. When this happens, emitter 44 and base 43 become shorted, with the result that a PN diode, rather than an open circuit, is formed between the two terminals of fuse device 40, i.e., emitter 44 and buried collector 41. The use of a vertical fuse device comprising a floating base bipolar transistor forming an open circuit when unprogrammed and which models a diode when programmed is depicted in FIG. 4b.
Vertical fuse arrays form a diode "AND" configuration, as shown in FIG. 5. Array 500 includes row line 501 and columns 503-1 through 503-N. Connected between row line 501 and columns 503-1 through 503-N are vertical fuse elements 502-1 through 502-N, respectively. Columns 503-1 through 503-N are applied with current from VCC terminal 504 through resistors 505-1 through 505-N, respectively. Transistors 506-1 through 506-N have their bases connected to columns 503-1 through 503-N, their collectors connected to VCC, and their emitters connected in common to the input lead of sense amplifier 507. In this manner, sense amplifier 507 provides an output signal on output lead 510 indicating whether all of fuses 502-1 through 502-N have been programmed (i.e., changed from an open circuit to a diode providing a short circuit between columns 503-1 through 503-N to row line 501). In other words, when any one or more of fuses 502-1 through 502-N remain unprogrammed (open circuit), the associated column is not pulled low, turning on the associated one of transistors 506-1 through 506-N, and causing sense amplifier 507 to provide a logical one output signal on output lead 510. Conversely, when all of fuses 502-1 through 502-N are programmed to provide a short circuit between columns 503-1 through 503-N to row line 501, columns 503-1 through 503-N are all pulled low, thereby preventing any of transistors 506-1 through 506-N from turning on, causing sense amplifier 507 to provide a logical zero output signal on output lead 510.
As is the case with OR array 200 of FIG. 2, row line 501 must be driven by an input buffer circuit. Row line 501 can be driven by input buffer circuit 300 of FIG. 3, but only if pull down current source 312 is made sufficiently large. For example, in the AND array of FIG. 5, the current flowing from each column 503-1 through 503-N through a programmed fuse 502-1 through 502-N to row line 501 is approximately 0.5 milliamps. For a typical PLA array having approximately 64 columns, each row line must sink between 15 to 30 milliamps. However, typical PLA devices include a plurality of row lines allowing for greater sophistication of the PLA. For a typical PLA having 16 row lines, the current drain for the 16 current sources alone is approximately 240 to 480 milliamps, a considerable amount of power. Accordingly, there arises the need for minimizing the power consumption of ECL PLAs utilizing an AND array of fuse devices.